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Table A–9. Shared Bus Table (Part 3 of 3)
NET Name
NET
Description
PLD (U60)
Flash (U5)
SRAM (U35)
SRAM (U36)
Ethernet (U4)
Pin
Name
Pin #
Pin
Name
Pin #
Pin
Name
Pin #
Pin
Name
Pin #
Pin
Name
Pin #
FLASH_CS_n
FLASH_OE-N
FLASH_RW-N
FLASH_WP_N
FLASH _BYTE_N
FLASH_RESET_N
FLASH_RY-BY_N
Chip Select
Read Enable
Write Enable
Write
Protect/ACC
Byte Enable
Reset
Ready/Busy
IO
IO
IO
IO
IO
IO
AE4
AB9
AD6
Y6
AB11
AE6
CE_n
OE_n
WE_n
WE_n.ACC
BYTE_n
Reset_n
RY/BY_n
32
34
13
16
53
14
17
SRAM_BE_N0
SRAM_BE_N1
Byte Enable 0
Byte Enable 1
IO
IO
K20
K19
BE0#
BE1#
39
40
SRAM_BE_N2
SRAM_BE_N3
Byte Enable 2
Byte Enable 3
IO
IO
K22
K21
BE2#
BE3#
39
40
SRAM_CS_N
SRAM_OE_N
SRAM_WE_N
ENET_ADS_N
ENET_AEN
ENET_BE_N0
ENET_BE_N1
ENET_BE_N2
ENET_BE_N3
ENET_CYCLE_N
ENET_DATACS_N
ENET_INTRQ0
ENET_IOCHRDY
ENET_IOR_N
ENET_IOW_N
ENET_LCLK
ENET_LDEV_N
Chip Select
Read Enable
Write Enable
Address
Strobe
Address
Enable
Byte Enable 0
Byte Enable 1
Byte Enable 2
Byte Enable 3
Bus Cycle
Data Chip
Select
Interrupt
IO Char
Ready
Read
Write
Local Bus
Clock
Local Device
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
J19
J22
J21
AD2
AF10
AD8
AF9
Y11
W12
AC9
Y12
AD11
AD1
AC10
AE11
W11
Y7
CS_n
OE_n
WE_n
6
41
17
CS_n
OE_n
WE_n
6
41
17
ADS#
AEN
BE0#
BE1#
BE2#
BE3#
CYCLE#
DATACS
#
INTRO
ARDY
RD#
WR#
LCLK
LDEV#
37
41
94
95
96
97
35
34
29
38
31
32
42
45
ENET_RDYRTN_N Ready Return
IO
V12
RDYRTN
46
#
ENET_W_R_N
Write/Read
IO
AC8
W/R#
36
Note to Table A–9 :
(1)
This pin is NC for AM29LV128M but is provided for compatible devices that have the active pin A23.
Altera Corporation
July 2005
A–3
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